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| INTEGRATED CIRCUITS DATA SHEET SAA7385 Error correction and host interface IC for CD-ROM (SEQUOIA) Preliminary specification File under Integrated Circuits, IC01 1996 Jun 19 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) CONTENTS 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2 3 4 5 6 7 7.1 7.2 7.3 7.4 8 8.1 8.2 8.3 8.4 9 9.1 9.2 10 10.1 10.2 FEATURES General 53CF94 SCSI controller 80C32 high-speed microcontroller Front-end interface logic Buffer controller Hardware third-level error correction Additional product support GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION 80C32 microcontroller 53CF94 fast SCSI controller Input clock doubler Front-end MICROCONTROLLER INTERFACE Microcontroller interface status register Microcontroller interface command register Microcontroller interrupts Microcontroller RAM organization FRONT PANEL AND MISCELLANEOUS CONTROL SIGNALS S2B UART registers Miscellaneous control registers FRONT-END Minute Second Frame (MSF) addressing and header information Front-end status and control 11 11.1 11.2 11.3 11.4 11.5 11.6 12 13 14 15 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 16 17 17.1 17.2 17.3 17.4 18 19 BUFFER MANAGER SAA7385 Front-end to buffer manager interface Microcontroller to buffer manager interface ECC to buffer manager interface SCSI to buffer manager interface Miscellaneous buffer manager considerations 53CF94 related registers FRAME BUFFER ORGANIZATION SUMMARY OF CONTROL REGISTER MAP LIMITING VALUES OPERATING CHARACTERISTICS I2S-bus timing; data mode EIAJ timing; audio mode R-W timing (see Fig.15) C-flag timing (see Fig.16) S2B interface timing SCSI interface timing Microprocessor interface DRAM interface (the SAA7385 is designed to operate with standard 70 ns DRAMs) PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS 1996 Jun 19 2 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 1 1.1 FEATURES General 1.5 Buffer controller SAA7385 * Ten level arbitration logic * Utilizes low cost 70 ns DRAMs * Page mode DRAM access for high-speed error correction and SCSI data transfer * Data organization by 3 kbyte frames * 256 kbyte or 1 Mbyte DRAM supported. 1.6 Hardware third-level error correction * Single chip digital solution for an 8 x speed CD-ROM controller chip * 10 Mbytes/s NCR53CF94 equivalent SCSI controller included * High-speed 80C32 microcontroller with 256 x 8 scratch-pad SRAM included * High performance CD-ROM interface logic * 128 pin QFP package. 1.2 53CF94 SCSI controller * Third-level correction provides superior performance in unfavourable conditions * Full hardware error correction to reduce microcontroller overhead * Corrections are automatically written to the DRAM frame buffer. 1.7 Additional product support * Separate clock input to allow operation up to the maximum 10 Mbytes/s * Fast synchronous SCSI-2 compatible * 24-bit transfer counter for single transfers up to 16 Mbytes * High-speed 16-bit DMA interface to the buffer manager DRAM * On-chip 48 mA SCSI drivers * Software compatible with members of the 53C90 family * Allows for SCAM support. 1.3 80C32 high-speed microcontroller * All control registers mapped into 80C32 special function memory space * Dedicated S2B interface UART * Input clock synthesizer * Red book audio pass through. 2 GENERAL DESCRIPTION * 33.87 MHz full system speed operation * Three timers/event counters * Programmable full duplex serial channel * Eight general purpose microcontroller I/O pins * External program ROM. 1.4 Front-end interface logic The SAA7385 is a high integration ASIC that incorporates all of the digital electronics necessary to connect a CD decoder to a SCSI host. An 80C32 microcontroller and a 53CF94 SCSI controller are embedded in the ASIC. The following functions are supported: * Input clock doubler * Block decoder * CRC checking of Mode 1 and Mode 2, Form 1 sectors * Red book audio pass through to SCSI * Buffer manager * Third-level error correction * Sub-code and Q-channel support * Dedicated S2B interface UART * Embedded 80C32 microcontroller * Embedded 53CF94 SCSI controller. * Full 8 x speed hardware operation * Block decoder * Sector sequencer * CRC checking of Mode 1 and Mode 2, Form 1 sectors * 212 ms watch-dog timer * Sub-code interface with synchronization * C-flag interface for absolute time stamp. 1996 Jun 19 3 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) The SAA7385 uses a 33.8688 MHz clock and is capable of accepting data at eight times (n = 8 or 1.4 Mbytes/s) the normal CD-ROM data rate. Third level error correction hardware is included to improve the correction efficiency of the system. The buffer manager hardware utilizes a ten-level arbitration unit and can stop the clock to the microcontroller to emulate a wait condition when necessary. The SAA7385 comprises five major functional blocks: * The 80C32 microcontroller is an industry standard core * The 53CF94 is an industry standard core * The front-end block connects to the external CD-60 based decoder and fully processes the incoming data stream to provide bytes of data that are stored in the external buffer * The buffer manager block provides the address generation and timing control for the external DRAM buffer * The ECC block performs the error correction functions in hardware on the data in the DRAM buffer. 3 QUICK REFERENCE DATA SYMBOL VDD Tamb Tstg 4 PARAMETER digital supply voltage operating ambient temperature storage temperature 4.5 0 -55 MIN. - - TYP. 5.0 SAA7385 Supply of this Compact Disc IC does not convey an implied license under any patent right to use this IC in any Compact Disc application. MAX. 5.5 70 +150 V UNIT C C ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION SOT387-2 SAA7385GP SQFP128 plastic quad flat package; 128 leads (lead length 1.6 mm); body 14 x 20 x 2.8 mm 1996 Jun 19 4 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 5 BLOCK DIAGRAM SAA7385 handbook, full pagewidth 256K x 8 or 1M x 8 DRAM BUFFER BUFFER MANAGER data subcode LAYERED ERROR CORRECTOR BUFFER MAPPER 53CF94 SCSI SCSI interface DATA CONVERTER AND SUB-CODE UART data CD DECODER subcode C-flag MICROCONTROLLER INTERFACE SERVO PROCESSOR S2B serial interface 80C32 MICROCONTROLLER DEBUG UART debug UART SAA7385 MGE388 64K x 8 ROM Fig.1 Block diagram (simplified). 6 PINNING All input, output and bidirectional signals are TTL level unless otherwise stated (Pull-Down = PD25 = 25 A; Pull-Up = PU25 = 25 A, PU400 = 400 A; Slew = S2 = 2 mA, S4 = 4 mA; CMOS slew = CMOS S2 = CMOS 2 = 2 mA; SCSI pad = SCSI = 48 mA). SYMBOL DA2 DA3 DA4 VSS1 DA5 DA6 DA7 DA8 DA9 VDD1 1996 Jun 19 PIN 1 2 3 4 5 6 7 8 9 10 I/O O O O - O O O O O - PAD S4 S4 S4 - S4 S4 S4 S4 S4 - DESCRIPTION DRAM address bus; bit DA2 DRAM address bus; bit DA3 DRAM address bus; bit DA4 ground 1 DRAM address bus; bit DA5 DRAM address bus; bit DA6 DRAM address bus; bit DA7 DRAM address bus; bit DA8 DRAM address bus; bit DA9 power supply 1 5 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) SYMBOL RAS CAS DWR DOE VSS2 DD0 DD1 DD2 DD3 VDD2 DD4 DD5 DD6 DD7 VSS3 LED TRAYSW EJECT LQDATA LWCLK VSS4 SCLK VSS5 SYSRES CFLAG CPR SPR SKIPFWD SKIPBACK SCSICLK VDD3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VSS6 LA0 1996 Jun 19 PIN 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 I/O O O O O - I/O I/O I/O I/O - I/O I/O I/O I/O - O I I O O - O - O I O I I I I - I/O I/O I/O I/O I/O I/O I/O I/O - O PAD S4 S4 S4 S4 - DESCRIPTION DRAM row address section; active LOW DRAM column address selection; active LOW DRAM write; active LOW DRAM output enable; active LOW ground 2 SAA7385 4 mA, Schmitt, PD25 DRAM data bus; bit DD0 4 mA, Schmitt, PD25 DRAM data bus; bit DD1 4 mA, Schmitt, PD25 DRAM data bus; bit DD2 4 mA, Schmitt, PD25 DRAM data bus; bit DD3 - power supply 2 4 mA, Schmitt, PD25 DRAM data bus; bit DD4 4 mA, Schmitt, PD25 DRAM data bus; bit DD5 4 mA, Schmitt, PD25 DRAM data bus; bit DD6 4 mA, Schmitt, PD25 DRAM data bus; bit DD7 - 24 mA, CMOS test Schmitt, PU25 Schmitt, PU25 2 mA 2 mA - 2 mA - 2 mA, PU25 Schmitt, PU400 2 mA Schmitt Schmitt, PU25 Schmitt, PU25 standard - S4, Schmitt S4, Schmitt S4, Schmitt S4, Schmitt S4, Schmitt S4, Schmitt S4, Schmitt S4, Schmitt - CMOS S2, PU25 ground 3 panel LED; active LOW; WTGCTL(4) active LOW when tray is in opens tray; active LOW serial data to DAC word strobe to DAC ground 4 data serial clock ground 5 system reset; OR of POR, SCSIRST and watch-dog timer C1 and C2 status S2B interface ready to accept data; active LOW S2B interface ready to send data; active LOW skip forwards; active LOW; RDSW(3) skip backwards; active LOW; RDSW(2) SCSI interface clock power supply 3 microcontroller multiplexed data bus; bit AD0 microcontroller multiplexed data bus; bit AD1 microcontroller multiplexed data bus; bit AD2 microcontroller multiplexed data bus; bit AD3 microcontroller multiplexed data bus; bit AD4 microcontroller multiplexed data bus; bit AD5 microcontroller multiplexed data bus; bit AD6 microcontroller multiplexed data bus; bit AD7 ground 6 EPROM latched lower address; bit LA0 6 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) SYMBOL LA1 LA2 LA3 VDD4 LA4 LA5 LA6 LA7 VSS7 A8 A9 A10 A11 A12 A13 A14 A15 PSEN VSS8 IO REQ CD SEL VSS9 MSG ACK BSY VSS10 ATN VDD5 SDP SD7 SD6 SD5 VSS11 SD4 SD3 SD2 SD1 SD0 VSS12 1996 Jun 19 PIN 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 I/O O O O - O O O O - O O O O O O O O O - I/O I/O I/O I/O - I/O I/O I/O - I/O - I/O I/O I/O I/O - I/O I/O I/O I/O I/O - PAD CMOS S2, PU25 CMOS S2, PU25 CMOS S2, PU25 - CMOS S2, PU25 CMOS S2, PU25 CMOS S2, PU25 CMOS S2, PU25 - CMOS S2, PU25 CMOS S2, PU25 CMOS S2, PU25 CMOS S2, PU25 CMOS S2, PU25 CMOS S2, PU25 CMOS S2, PU25 CMOS S2, PU25 CMOS 2, PU25 - SCSI SCSI SCSI SCSI - SCSI SCSI SCSI - SCSI - SCSI SCSI SCSI SCSI - SCSI SCSI SCSI SCSI SCSI - DESCRIPTION EPROM latched lower address; bit LA1 EPROM latched lower address; bit LA2 EPROM latched lower address; bit LA3 power supply 4 EPROM latched lower address; bit LA4 EPROM latched lower address; bit LA5 EPROM latched lower address; bit LA6 EPROM latched lower address; bit LA7 ground 7 EPROM upper address; bit A8 EPROM upper address; bit A9 EPROM upper address; bit A10 EPROM upper address; bit A11 EPROM upper address; bit A12 EPROM upper address; bit A13 EPROM upper address; bit A14 EPROM upper address; bit A15 program store enable; active LOW ground 8 SCSI phase signal, active LOW SCSI request, active LOW SCSI phase signal, active LOW SCSI select, active LOW ground 9 SCSI phase signal, active LOW SCSI acknowledge, active LOW SCSI busy, active LOW ground 10 SAA7385 output in initiator mode; input in target mode, active LOW power supply 5 SCSI parity, active LOW SCSI data bus; bit SD7 SCSI data bus; bit SD6 SCSI data bus; bit SD5 ground 11 SCSI data bus; bit SD4 SCSI data bus; bit SD3 SCSI data bus; bit SD2 SCSI data bus; bit SD1 SCSI data bus; bit SD0 ground 12 7 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) SYMBOL RXS2B TXS2B TRAYIN TRAYOUT SCSIRST POR VDD6 UC_PORT1.7 RAB_MUSB NRST_SEQ UC_PORT1.4 UC_PORT1.3 UC_PORT1.1 HOMESW PLAY UC_PORT1.6 VSS13 GPI1 GPI2 KILL TXICE RXICE RXSUB VDD7 OSCIN VSS14 CLAB VSS15 DAAB WSAB EFAB CLK34 TEST VSS16 DA0 DA1 PIN 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 I/O I O I/O I/O I I - I/O I/O I/O I/O I/O I/O I/O I I/O - I I I O I I - I - I - I I I O I - O O PAD Schmitt, PU25 4 mA 4 mA, PD25 4 mA, PD25 Schmitt CMOS - CMOS 2, PU25 CMOS 2, PU25 CMOS 2, PU25 CMOS 2, PU25 CMOS 2, PU25 CMOS 2, PU25 2 mA, PU25 Schmitt CMOS 2, PU25 - Schmitt, PU25 Schmitt, PU25 Schmitt, PU25 4 mA Schmitt, PU25 Schmitt, PU25 - standard - Schmitt - Schmitt Schmitt Schmitt 2 mA Schmitt, PD25 - S4 S4 S2B interface receive S2B interface transmit DESCRIPTION SAA7385 tray extend control; active LOW (general purpose signal) tray retract control; active LOW (general purpose signal) SCSI reset, active LOW; also causes a system reset power-on reset; active LOW power supply 6 drive speed select; microcontroller port 1.7 RD/WR, acknowledge; microcontroller port 1.2 reset to engine; microcontroller port 1.5 general purpose microcontroller I/O port; port 1.4 general purpose microcontroller I/O port; port 1.3 general purpose microcontroller I/O port; port 1.1 actuator sled home; active LOW; microcontroller port 1.0 laser on and focused status; active LOW; RDSW(4) general purpose microcontroller I/O port; port 1.6 ground 13 general purpose input; microcontroller port 3.4 general purpose input; microcontroller port 3.5 shut off audio; active LOW debug UART output; from 80C32 serial port debug UART input; to 80C32 serial port sub-code input power supply 7 master input clock; 34 or 16 MHz ground 14 clock ground 15 data word strobe error flag 34 MHz output clock test pin; must be ground ground 16 DRAM address bus; bit DA0 DRAM address bus; bit DA1 1996 Jun 19 8 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) SAA7385 101 RAB_MUSB 102 NRST_SEQ 96 TRAYOUT handbook, full pagewidth 100 UC_PORT1.7 97 SCSIRST 95 TRAYIN 93 RXS2B 94 TXS2B 92 VSS12 86 VSS11 80 ATN 79 VSS10 69 PSEN 81 VDD5 99 VDD6 75 VSS9 70 VSS8 76 MSG 72 REQ 98 POR 82 SDP 77 ACK 78 BSY 91 SD0 90 SD1 89 SD2 88 SD3 87 SD4 85 SD5 84 SD6 83 SD7 74 SEL 68 A15 67 A14 66 A13 65 A12 64 A11 63 A10 62 A9 61 A8 60 VSS7 59 LA7 58 LA6 57 LA5 56 LA4 55 VDD4 54 LA3 53 LA2 52 LA1 51 LA0 50 VSS6 49 AD7 48 AD6 47 AD5 46 AD4 45 AD3 44 AD2 43 AD1 42 AD0 41 VDD3 40 SCSICLK 39 SKIPBACK SKIPFWD 38 MGE387 73 CD UC_PORT1.4 103 UC_PORT1.3 104 UC_PORT1.1 105 HOMESW 106 PLAY 107 UC_PORT1.6 108 VSS13 109 GPI1 110 GPI2 111 KILL 112 TXICE 113 RXICE 114 RXSUB 115 VDD7 116 OSCIN 117 VSS14 118 CLAB 119 VSS15 120 DAAB 121 WSAB 122 EFAB 123 CLK34 124 TEST 125 VSS16 126 DA0 127 DA1 128 VDD1 10 RAS 11 CAS 12 DWR 13 DOE 14 VSS2 15 DD0 16 DD1 17 DD2 18 DD3 19 VDD2 20 DD4 21 DD5 22 DD6 23 DD7 24 VSS3 25 LED 26 TRAYSW 27 EJECT 28 LQDATA 29 LWCLK 30 VSS4 31 SCLK 32 VSS5 33 SYSRES 34 CFLAG 35 CPR 36 SPR 37 1 2 3 4 5 6 7 8 9 SAA7385 DA2 DA3 DA4 VSS1 DA5 DA6 DA7 DA8 DA9 Fig.2 Pin configuration. 1996 Jun 19 9 71 IO ndbook, full pagewidth 1996 Jun 19 HF signal focus and radial data OFF track TDA1305 TDA1308 DIGITAL SERVO CONTROL CD DECODER I2S I2S Q to W SCSI BLOCK DECODER INTERFACE SAA7385GP + 256K/1M DRAM EN XTAL RESET DATA CLOCK CDT663 OM5234/FBx SERVO CONTROL MICRO 64K (P)ROM S2B CDT665 MGE389 Philips Semiconductors sledge home switch CDM 12.6 DAC AUDIO PROCESSOR right output left output DIODE AMPLIFIER LASER SUPPLY laser on OQ8868 LO9585 3-BEAM MECHANISM OQ8866 laser drive single/double/ quadruple speed Error correction and host interface IC for CD-ROM (SEQUOIA) 10 DIGITAL SERVO DRIVERS OQ8844 + TDA7072A(T) sledge drive radial servo SCSI-2 interface with fast synchronous and SCAM focus servo motor drive L1266 loader in CD LOADER loader out loader status Preliminary specification SAA7385 Fig.3 Example of CD-ROM system with SCSI-2 interface. Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 7 7.1 FUNCTIONAL DESCRIPTION 80C32 microcontroller 7.4.2 SECTOR SEQUENCER SAA7385 The standard specification for details of the operation for this part may be found in any data sheet covering the 80C32 microcontroller. The one deviation from a normal 80C32 is the addition of all of the control registers for the special function register map for the 80C32. All of the SAA7385 control registers, including the 53CF94 control registers appear within this space. 7.2 53CF94 fast SCSI controller The sector sequencer de-serializes the data and error flags from the block decoder and determines when to: * Write data to the buffer * Write flags to the buffer * Test the header to determine the Mode * Test the sub-header to determine the Form * Test the CRC * End the sector and write the status byte to the buffer. Included in the sector sequencer is the CRC generator which checks each Yellow Book or Green Book sector as it is shifted into the SAA7385 in accordance with the following polynomial: X32 + X31 + X16 + X15 + X4 + X3 + X + 1 The status of each sector is saved and written to the buffer at the end of the sector. 7.4.3 SUB-CODE RECEIVE AND Q-CHANNEL EXTRACTOR The details of operation of this block may be found in the "53CF94 data manual". Two deviations from the operation of a normal 53CF94 have been made. The first is that the part supports single-ended SCSI bus operation only. The second deviation is the additional feature of mapping the control registers into the 80C32 special function register map as previously mentioned. 7.3 Input clock doubler To facilitate compatibility of the SAA7385 with the maximum number of CD decoders, a clock doubler has been included. This clock doubler may take a 16.9344 MHz clock and double this when requested to do so by the microcontroller. Logic has been included to remove the possibility of a `runt' clock pulse when the doubler is engaged. Once engaged, the only way to disengage it is via a reset condition. 7.4 Front-end A UART which samples asynchronous bits on a 24 clocks per bit basis is included. This is required because Philips decoders output the sub-code data at nominally 24 clocks per bit, but not synchronized to the data. Also included is a sub-code synchronization detector which senses the beginning of each new sector of sub-code information. The serial sub-code information is assembled into bytes in the following order: Data bits 7 to 0 = 0, Q, R, S, T, U, V and W. The front-end is comprised of many sub-sections. 7.4.1 BLOCK DECODER The block decoder first reverses the bits of each received byte and then runs them through a linear feedback shift register to be de-scrambled. The polynomial used to de-scramble the serial data is as follows: X15 + X + 1 It also detects and tests the synchronization field and will start the data clock when commanded. The de-scrambled header is assembled into four registers (MODE, MINS, SECS and FRMS) with header ready and header error status (see HDRRDY and HDRERR in RDDSTAT). The data clock does not have to be enabled to receive valid headers. Also included in this section is the logic required to decide when to start collecting data and sub-code information taken from the synchronization signal. As each byte is assembled, it is sent to the buffer manager to be written to the DRAM buffer. At the same time, the Q-channel bits are assembled into bytes and sent to the buffer. All Q-channel bytes except CRC are sorted in registers for use by the microcontroller. The track, mode, minutes, seconds and frames bytes (RDTK, RDMD, RDMN, RDSC and RDFM) are also stored in registers for use by the microcontroller. The Q-channel CRC (last two bytes) is checked just before the end of the sub-code sector. If the CRC check fails, BADQ in RDDSTAT is available to the microcontroller and is written into the buffer at the end of the sector. When the five Q-channel registers have been updated, QFRMRDY in RDDSTAT is set. The five Q-channel registers are valid while QFRMRDY is set. In the audio mode, HDRRDY in RDDSTAT generates this interrupt, but the QFRMRDY bit will still be available as status to the microcontroller. 1996 Jun 19 11 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 7.4.4 C-FLAG RECEIVER 7.4.8 BUFFER MANAGER SAA7385 The C-flag bits, or corrector flags, are also 24 data clocks long and reception of these bits is achieved using the same method as for the sub-code; in this event, the C-flag data is synchronized to the data. The difference is that only one bit is used; F1, the absolute time synchronization information. When in audio mode and ENABRED in FECTL is set, receipt of F1 set will start the internal data clock after the next rising edge of word strobe (WSAB) which is the left channel sample when the CD decoder is programmed for EIAJ audio format. When in audio mode, the Q-channel information provides the MSF address and the F1 flag provides the start of frame information; together these provide an absolute byte address on the disc. 7.4.5 S2B UART The buffer manager provides the arbitration for the different processes that wish to access the DRAM buffer. These processes include the front-end, microcontroller requests, ECC accesses, SCSI interface requests and DRAM refreshing. The DRAM control logic will start an access on the next rising edge of the clock after a request is received. If two or more requests are pending then the priority is as follows: 1. Front-end (highest priority) 2. Microcontroller requests 3. SCSI interface requests 4. ECC requests (lowest priority). A refresh cycle is required every 15.6 s and will be granted priority for one access. A burst access by ECC or SCSI will only be interrupted by a higher priority access request. In addition to the priority logic, logic is required for the front-end sources of data. The priority is: frame data (highest), flag data, sub-code data, Q-channel data and finally status byte. All front-end sources are granted priority over the SCSI logic, ECC, refresh and data will be written into the frame store during the next cycle. However, the microcontroller has priority over the lower three front-end sources and will be granted an access after front-end frame data or flag data is written to memory. The required timing (see Figs 4 to 11) operate with the industry standard 70 ns DRAMs. The interface is designed to operate with one or two DRAMs using: 256 kbit x 4 or 1 Mbit x 4 devices. If a single DRAM is connected, all access cycles require a page mode cycle to load both the high and the low nibble of data. With a byte-wide memory attached, a single byte cycle takes five clock cycles of 29.5 ns each, totalling 147.5 ns. In nibble mode, a single byte cycle takes 236 ns. This UART is provided for remote debugging of the firmware. It is hard-wired for one start-bit, eight data bits, a parity bit and one stop bit. Parity testing can be programmed to be either odd parity or even parity. Parity error and over-run status are provided via PE and OVRRUN in S2BSTAT. Selectable baud rates of 31.25, 62.5 and 187.5 kbaud are available via ICESEL1 and ICESEL0 in BRGSEL. 7.4.6 WATCH-DOG TIMER A pair of counters are included which output a 967 s reset pulse to the entire chip and the SYSRES pin if the timer is not reset during the 212 ms time-out period. The watch-dog timer is reset by setting RWMD in FECTL HIGH then LOW. If RWMD is left HIGH, the watch-dog function is disabled. 7.4.7 GLUE LOGIC (GLIC) The final block of logic in the front-end consists of: a programmable, linear pulse-width modulator for spindle-motor control; an address de-multiplexer for the address/data bus of the microcontroller; plus audio multiplexing and muting circuitry for full control of Red Book audio data to an external Digital-to-Analog Converter (DAC). 1996 Jun 19 12 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) SAA7385 handbook, full pagewidth CLOCK RAS CAS ADDRESS DATA ROW COL latch low nibble COL latch high nibble DOE MGE390 Fig.4 Nibble access read cycle. handbook, full pagewidth CLOCK RAS CAS ADDRESS DATA ROW COL low-nibble COL high-nibble WRITE MGE391 Fig.5 Nibble access write cycle. 1996 Jun 19 13 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) SAA7385 handbook, full pagewidth CLOCK RAS CAS ADDRESS DATA ROW COL latch data DOE MGE392 Fig.6 Byte mode single access read cycle. handbook, full pagewidth CLOCK RAS CAS ADDRESS DATA ROW COL DATA WRITE MGE393 Fig.7 Byte mode single access write cycle. 1996 Jun 19 14 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) SAA7385 handbook, full pagewidth CLOCK RAS CAS ADDRESS DATA ROW COL1 latch COL2 latch COL3 latch COL4 DOE MGE394 Fig.8 ECC burst access read cycle. handbook, full pagewidth CLOCK RAS CAS ADDRESS DATA ROW COL1 DATA1 COL2 DATA2 COL3 DATA3 COL4 DATA4 WRITE MGE395 Fig.9 ECC burst access write cycle. 1996 Jun 19 15 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) SAA7385 handbook, full pagewidth CLOCK RAS CAS ADDRESS DATA ROW COL1 latch data COL2 latch data COL3 COL4 latch data DOE MGE396 Fig.10 SCSI standard burst access read cycle. handbook, full pagewidth CLOCK RAS CAS ADDRESS DATA ROW COL1 DATA1 COL2 DATA2 COL3 DATA3 COL4 DATA4 WRITE MGE397 Fig.11 SCSI standard burst access write cycle. 1996 Jun 19 16 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 8 8.1 MICROCONTROLLER INTERFACE Microcontroller interface status register NUM_COR register: 0xF08E DATA BYTE MNEMONIC NUM_COR R/W 7 R 6 5 4 3 2 1 SAA7385 Table 1 0 NUM_COR7 to NUM_COR0 Register 0xF08E indicates the number of corrections performed during the most recently executed CORRECT_P_SYNDROMES or CORRECT_Q_SYNDROMES command. Note that NUM_COR is only valid after completion of the CORRECT_P_SYNDROMES or CORRECT_Q_SYNDROMES command, and becomes invalid upon execution of any other command. Table 2 ECC_STATUS register: 0xF086 DATA BYTE MNEMONIC ECC_STATUS R/W 7 R - 6 - 5 - 4 3 2 PS_EQ0 1 QS_EQ0 0 ECC_ACT FLG_EQ0 CRC_EQ0 Register 0xF086 provides status information on the current or last ECC command. Table 3 ECC_STATUS definitions DESCRIPTION asserted while a command other than ASSERT_ABORT or RELEASE_ABORT remains active asserted when all Q syndromes are zero asserted when all P syndromes are zero asserted when the CRC remainder calculated by the CRC_CALCULATE command is all zeros asserted when all flag bytes in ECC RAM are zero MNEMONIC ECC_ACT QS_EQ0 PS_EQ0 CRC_EQ0 FLG_EQ0 8.2 Microcontroller interface command register ECCCTL register: 0xF085 DATA BYTE R/W 7 ECCCTL R/W - 6 - 5 - 4 - 3 2 1 0 ECC_COMMAND3 to ECC_COMMAND0 Table 4 MNEMONIC The ECC_COMMAND definitions are explained in Table 5. 1996 Jun 19 17 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) Table 5 Definitions of ECC_COMMAND3 to ECC_COMMAND0 DESCRIPTION ASSERT_ABORT RELEASE_ABORT CALCULATE_SYNDROMES (not Mode 2, Form 1) CALCULATE_SYNDROMES (Mode 2, Form 1) CRC_RECALCULATE (not Mode 2, Form 1) CRC_RECALCULATE (Mode 2, Form 1) COPY_RESULTS (not Mode 2, Form 1) COPY_RESULTS (Mode 2, Form 1) CORRECT_P_SYNDROMES CORRECT_Q_SYNDROMES TEST_ECC_ROM TEST_ECC_RAM_READ TEST_ECC_RAM_WRITE SAA7385 EEC_COMMAND 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1100 1101 1110 Table 6 Command descriptions COMMAND ASSERT_ABORT DESCRIPTION Terminates any currently active operation and re-initializes the ECC logic. Remains in reset state until occurrence of the RELEASE_ABORT command. At power-on reset, the ECC is in the ASSERT_ABORT state. All microcontroller status bits are reset when the ECC is in the ASSERT_ABORT state. Terminates the ASSERT_ABORT command and enables activation of other commands. Calculate CRC remainder buffer data, storing result in ECC RAM and updating microcontroller status bit CRC_EQ0. Mode 2, Form 1 uses address 16 : 2075, or 0 : 2067; note 1. Prepares buffer for correction, calculates P and Q syndromes, and copies error flags and CRC remainder from buffer to ECC RAM. The microcontroller status bits PS_EQ0, QS_EQ0 and FLAGS_EQ0 are updated at the end of this operation. 1. Copy header from buffer to ECC RAM (Mode 2, Form 1 only) 2. Write to the buffer. Not Mode 2, Form 1: Address 0 0x00; Address 1 : 10 0xFF; Address 11 0x00; Address 2068 : 2075 0x00 Mode 2, Form 1: Address 0 0x00; Add 1 : 10 0xFF; Add 11 : 15 0x00 3. Read header and frame data from buffer to calculate P and Q syndromes psyn[0 : 85].s1, psyn[0 : 85].s0, qsyn[0 : 51].s1 and qsyn[0 : 51].s0, storing results in ECC RAM; see Table 76 4. Copy error flags from buffer to ECC RAM 5. Copy CRC remainder from buffer to ECC RAM 6. Update microcontroller status bits PS_EQ0, QS_EQ0 and FLAGS_EQ0. RELEASE_ABORT CRC_RECALCULATE CALCULATE_SYNDROMES 1996 Jun 19 18 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) COMMAND COPY_RESULTS DESCRIPTION Copies current ECC RAM contents to the buffer memory: SAA7385 1. Copy header flags from ECC RAM to buffer (Mode 2, Form 1 only) 2. Copy error Flags from ECC RAM to buffer 3. Copy CRC remainder from ECC RAM to buffer 4. Copy P syndromes from ECC RAM to buffer 5. Copy Q syndromes from ECC RAM to buffer. CORRECT_P_SYNDROMES Scan all P syndromes and perform P-syndrome calculation. The microcontroller status bits PS_EQ0, QS_EQ0 and FLAGS_EQ0 are updated at the end of this operation. Scan all Q syndromes and perform Q-syndrome calculation. The microcontroller status bits PS_EQ0, QS_EQ0 and FLAGS_EQ0 are updated at the end of this operation. Read each exponent and log in the alpha ROM to the NUM_COR register. This command may only be terminated by the ASSERT_ABORT command. Read ECC RAM addresses 0 : 591 and copy to buffer addresses 0 : 591. Read buffer addresses 0 : 591 and copy to ECC RAM addresses 0 : 591. CORRECT_Q_SYNDROMES TEST_ECC_ROM TEST_ECC_RAM_READ TEST_ECC_RAM_WRITE Note 1. 16 : 2075 and 0 : 2067 are address frame offsets. The frame buffer organization is shown in Table 75. 8.3 Microcontroller interrupts An interrupt pulse is generated upon completion of any of the following commands: * CALCULATE_SYNDROMES (not Mode 2, Form 1) * CALCULATE_SYNDROMES (Mode 2, Form 1) * CRC_RECALCULATE (not Mode 2, Form 1) * CRC_RECALCULATE (Mode 2, Form 1) * COPY_RESULTS (not Mode 2, Form 1) * COPY_RESULTS (Mode 2, Form 1) * CORRECT_P_SYNDROMES * CORRECT_Q_SYNDROMES * TEST_ECC_ROM * TEST_ECC_RAM_READ * TEST_ECC_RAM_WRITE. If a command is aborted by the ASSERT_ABORT command, a spurious interrupt may be generated within five clock cycles of the ASSERT_ABORT command. 1996 Jun 19 19 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) Table 7 Command execution times COMMAND CALCULATE_SYNDROMES (not Mode 2, Form 1) CALCULATE_SYNDROMES (Mode 2, Form 1) CRC_RECALCULATE (not Mode 2, Form 1) CRC_RECALCULATE (Mode 2, Form 1) COPY_RESULTS (not Mode 2, Form 1) COPY_RESULTS (Mode 2, Form 1) CORRECT_P_SYNDROMES (maximum addition per correction) CORRECT_Q_SYNDROMES (maximum addition per correction) TEST_ECC_RAM_READ TEST_ECC_RAM_WRITE CYCLES 5604 5600 4136 4120 1148 1156 1466 157 888 167 1184 1184 TIME (s) at 33 MHz 186.8 186.7 137.9 137.3 38.3 38.5 48.9 5.2 29.6 5.6 39.5 39.5 SAA7385 MEMORY ACCESSES 2658 2654 2068 2060 574 578 0 2 0 2 592 592 All times indicated reflect two clock cycles per memory access for all accesses other than P and Q corrections. P and Q corrections reflect seven clock cycles per memory access. Execution times will be extended due to refresh timing, other buffer traffic, and configuration of nibble-wide memory. 8.3.1 INTERRUPT REGISTER DEFINITIONS Two registers are used to control the operation of the interrupt logic. The register INTRMSK allows each interrupt to be enabled or disabled. INTRMSK and INTRFLG are cleared on reset to initially disable and clear all interrupts; the output latch controlling the INT line is set on a reset; this must be cleared by writing 0x00 to INTRFLG. To enable an interrupt, the bit that corresponds to the interrupt in INTRFLG must be set. The INTRFLG register shows the status of the interrupts. If any bit is HIGH then an interrupt has occurred since the last time the bit was cleared. Writing a zero to any bit location in INTRFLG will clear the corresponding interrupt. If a masked interrupt occurs, the microcontroller can still detect the occurrence because the event is still posted in INTRFLG. Table 8 Interrupt mask register: 0xF0FB DATA BYTE MNEMONIC INTRMSK R/W 7 R/W MASK7 6 MASK6 5 MASK5 4 MASK4 3 MASK3 2 MASK2 1 MASK1 0 MASK0 Each bit in register 0xF0FB corresponds to the interrupt at the same bit location in register 0xF0FC. To enable an interrupt, the bit in this register must be set HIGH. Table 9 Interrupt flag register: 0xF0FC DATA BYTE MNEMONIC INTRFLG R/W 7 R/W - 6 FETXINT 5 FERXINT 4 3 2 FE2352 1 0 ECC_COR FE_HDR STR_LST FRM_STR If any bit is set in this register (Table 9) then an interrupt may be sent to the microcontroller. Table 10 shows when the interrupts are asserted; assuming the corresponding mask bit is set. 1996 Jun 19 20 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) Table 10 INTRFLG field descriptions FIELD FRM_STR STR_LST FE_2352 FE_HDR ECC_COR RFERXINT FETXINT 8.4 set at the start of the last frame set if the front-end data exceeds 2352 bytes front-end interrupt for header (or Q channel) ready ECC interrupt for correction complete front-end interrupt for receive ready front-end interrupt for transmit ready DESCRIPTION set one when one complete frame is stored SAA7385 Microcontroller RAM organization MICFRM# is used to determine the frame address for the microcontroller access through the frame window 0x8000 to 0x8FFF. To obtain the actual byte location within the buffer RAM, the lower 12 bits of the microcontroller address form the relative offset and hence the absolute address is found. Note that the microcontroller has the option of addressing memory in a linear fashion using the 32 kbyte address space between 0x000 and 0x7FFF. If this 32 kbyte page is used, the PAGEREG must be programmed with the required page address. PAGEREG is used to select the required page when the microcontroller makes a linear access to the buffer memory using the address space 0x7000 to 0x7FFF. The actual address is the fifteen LSBs from the microcontroller plus 32768 times the value in PAGEREG. Table 11 Microcontroller frame number address registers: 0xF0F6 and 0xF0F7 DATA BYTE MNEMONIC MICFRM# MICFRM# R/W 7 R/W R/W NUM7 - 6 NUM6 - 5 NUM5 - 4 NUM4 - 3 NUM3 - 2 NUM2 - 1 NUM1 - 0 NUM0 NUM8 Registers 0xF0F6 and 0xF0F7 provide the frame number address for the microcontroller access to memory. The counter associated with these registers is loaded after the most significant byte is written; the least significant byte must be written first to ensure that the counter is loaded correctly. If a DRAM access is in progress that uses the address from the counter, the update will be delayed until the access is complete. 1996 Jun 19 21 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) Table 12 Microcontroller address page register: 0xF0FF DATA BYTE MNEMONIC PAGEREG Note 1. PAGE_EN is disconnected. R/W 7 R/W - 6 - 5 PAGE_EN(1) 4 MA_19 3 MA_18 2 MA_17 SAA7385 1 MA_16 0 MA_15 Register 0xF0FF is used by the buffer manager for the upper address lines when the microcontroller addresses non-frame memory. These registers overlap frame memory, so register 0xF0FF must be programmed with an address in the top part of the memory if no overlap is required. The microcontroller page address line is selected from this register. The outputs are used directly to control DRAM access cycles, and will affect any current DRAM cycle in progress. It is possible to access three contiguous frames from the microcontroller by reading the three data sector windows, 0x8000 to 0x8FFF, 0x9000 to 0x9FFF and 0xA000 to 0xAFFF. This function is required for the decoding of the sub-code information. If the `next' frame wraps past the last frame pointer (LASTFRM) then the pointers are modified to wrap back to the start pointer onwards (FEFRM#); this section is transparent to the microcontroller. Table 13 Program memory control register: 0xF09F DATA BYTE MNEMONIC PRGMEM R/W 7 R/W 6 5 SEL_TOP 4 INV_A15 3 - 2 - 1 - 0 - DATAPRG EN_WIN Register 0xF09F controls a system test feature where an SRAM is used for the 80C32 external program memory; note DATAPRG must be set for any of these features to be enabled. Table 14 PRGMEM field descriptions FIELD INV_A15 SEL_TOP EN_WIN DATAPRG LOGIC 0 1 0 1 0 1 0 1 normal operation invert A(15) to program memory for data memory access select bottom 32 kbyte window select top 32 kbyte window windowing disabled 32 kbyte windows are enabled and SEL_TOP is used to determine window selected normal operation data memory is mapped to program memory and data memory DRAM accesses are disabled DESCRIPTION 1996 Jun 19 22 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) SAA7385 handbook, halfpage 0000 80C32 SCRATCH PAD RAM 7FFF 8000 DATA SECTOR WINDOW (FRAME 0) DATA SECTOR WINDOW (FRAME 1) DATA SECTOR WINDOW (FRAME 2) 9000 A000 AFFF F000 FFFF SAA7385 CONTROL REGISTERS MGE398 Fig.12 Address map for the microcontroller. Table 15 SAA7385 address map details for the 80C32 ADDRESS 0000 to 7FFF FUNCTION This 32 kbyte window is used to address and portion the DRAM buffer. It is intended for non-frame mapped memory to be addressed through this window. The upper page address bits (to address the full range of the DRAM buffer) are set by the linear address page register (PAGEREG). All accesses to frame memory use this window to read or write to the buffer memory. The actual address to the DRAM buffer is Micro Frame Number (MICFRM#) times 3 k plus the 12 LSBs from the 80C32. This frame window is identical to the frame 0 window with the exception that one is added to the value from the Micro Frame Number (MICFRM#). This frame window is identical to the frame 0 window with the exception that two is added to the value from the Micro Frame Number (MICFRM#). Not used; outputs are driven LOW SAA7385 control registers 23 8000 to 8FFF 9000 to 9FFF A000-AFFF B000-EFFF F000-FFFF 1996 Jun 19 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 9 FRONT PANEL AND MISCELLANEOUS CONTROL SIGNALS SAA7385 This chapter describes the various SAA7385 control signals; front panel and basic engine signals, jumper settings and use of the general purpose signals. Table 16 Start clock doubler: 0xF091 DATA BYTE MNEMONIC CLKSEL R/W 7 W - 6 - 5 - 4 - 3 - 2 - 1 - 0 - A write of any value to this address will engage the clock doubler. The state of the doubler may be obtained by reading C_34_16 in BRGSEL (see Table 30). If this bit is set then the clock doubler is engaged. On power-on, the clock doubler is disabled. Once the clock doubler is engaged, it can only be reset by one of the reset sources; a power-on reset, a SCSI reset or a reset from the watch-dog timer. The clock doubler must not be engaged when a 33.8688 MHz clock is connected to OSCIN (pin 117). Table 17 Frequency synthesizer test register: 0xF0D8; note 1 DATA BYTE MNEMONIC FSTEST Note 1. Register 0xF0D8 is used for IC-level testing and to power down the frequency synthesizer. Only bit USE_IN should be asserted in normal operation. Table 18 FSTEST field description FIELD FS_LOCK FVCOD CPSEL USE_IN LOGIC 0 1 0 1 0 1 0 1 normal operation 3-state LED and switch LQDATA to FS_LOCK normal operation test mode for FVCOD from the synthesizer normal operation test mode for CPSEL from the synthesizer use internal synthesizer power down the synthesizer and operate off a 33.87 MHz input clock DESCRIPTION R/W 7 R/W - 6 - 5 USE_IN 4 CPSEL 3 FVCOD 2 FS_LOCK 1 - 0 - Table 19 Disconnected pulse-width modulator control: 0xF0B3; note 1 DATA BYTE MNEMONIC WTPWM Note 1. Register 0xF0B3 is disconnected. R/W 7 R/W - 6 - 5 - 4 - 3 - 2 - 1 - 0 - 1996 Jun 19 24 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) Table 20 General logic control register: 0xF0B9; note 1 DATA BYTE MNEMONIC WTGCTL Note 1. Register 0xF0B9 controls the audio mixing and the LED. Table 21 WTGCTL field description FIELD CHANNELS LOGIC 00 01 10 11 RA_MUTE LA_MUTE LED PWMSEL - - - - mute right data sent to both channels left data sent to both channels stereo right channel digital mute left channel digital mute active LOW control for the light emitting diode PWM is disconnected DESCRIPTION R/W 7 W - 6 - 5 PWMSEL 4 LED 3 2 1 SAA7385 0 LA_MUTE RA_MUTE CHANNEL1 CHANNEL0 Table 22 Drive switches register: 0xF0BA; note 1 DATA BYTE MNEMONIC RDSW Note 1. Register 0xF0BA is used for sensing the drive switches. Table 23 RDSW field description FIELD TRAYSW EJECT SKIPBACK SKIPFWD PLAY LOGIC 0 1 - - - - tray position in tray position out user is requesting the drive tray to open (active LOW) user is requesting a track skip backwards (active LOW) user is requesting a track skip forwards (active LOW) user is requesting the drive to play (active LOW) DESCRIPTION R/W 7 R - 6 - 5 - 4 PLAY 3 2 1 EJECT 0 TRAYSW SKIPFWD SKIPBACK Table 24 Jumper status register: 0xF0C9; note 1 DATA BYTE MNEMONIC RDJMPRS Note 1. The bit fields for the jumpers are explained in Table 25. 1996 Jun 19 25 R/W 7 R 6 5 4 3 2 1 0 JUMPER7 to JUMPER0 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) Table 25 RDJMPRS field description FIELD JUMPER7 to JUMPER0 DESCRIPTION SAA7385 Indicates the value of the DRAM data bus on power-up. The data bus may be pulled HIGH or LOW using weak pull-ups and pull-downs hence up to eight jumper settings are accommodated. Table 26 General purpose bits: 0xF0C2; note 1 DATA BYTE MNEMONIC GPIOCTL Note 1. Register 0xF0C2 controls the direction and output state of the general purpose I/O bits on the SAA7385. Reading the GPIO direction bits reflects the last value that was written to the register. The four GPIO data bits shows the current value of the input signals in the input mode. In the output mode, the last value written to the output latches is that which is read back. Table 27 GPIOCTL field description FIELD GPDIR1 GPDAT1 GPDIR2 GPDAT2 GPDIR3 GPDAT3 GPDIR4 GPDAT4 DESCRIPTION General purpose bit direction control. Default LOW puts GPIO1 into the input mode, setting this HIGH puts GPIO1 in output mode. GPIO1 data bit. General purpose bit direction control. Default LOW puts GPIO2 into the input mode, setting this HIGH puts GPIO2 in output mode. GPIO2 data bit. General purpose bit direction control. Default LOW puts GPIO3 into the input mode, setting this HIGH puts GPIO3 in output mode. GPIO3 data bit. General purpose bit direction control. Default LOW puts GPIO4 into the input mode, setting this HIGH puts GPIO4 in output mode. GPIO4 data bit. R/W 7 R/W GPDAT4 6 GPDIR4 5 GPDAT3 4 GPDIR3 3 GPDAT2 2 GPDIR2 1 GPDAT1 0 GPDIR1 1996 Jun 19 26 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 9.1 S2B UART registers SAA7385 This section describes the registers used for the S2B UART control. Table 28 S2B UART transmit, receive and status buffer: 0xF0A1, F0A2 and F0A3 DATA BYTE MNEMONIC WTS2B(1) RDS2B S2BSTAT Note 1. WTS2B is for the transmit data byte from the S2B UART and RDS2B is for the receive data byte from the S2B UART. Table 29 S2BSTAT field description FIELD RXDRDY OVRRUN PE TXDRDY CPR DESCRIPTION A logic 1 indicates that the receive data is valid. A logic 1 indicates that the data in the receive buffer was not read before it was over written by the next byte. A logic 1 indicates that a parity error was detected in the receive data byte; this is usually caused by the wrong baud rate. A logic 1 indicates that the transmit data buffer is empty and ready for another byte. S2B handshake bit which may be interpreted as `clear to send'; this is generated automatically by the UART. It is asserted whenever the UART receiver is ready for a byte and negated as soon as the stop bit is shifted in. It is again asserted as soon as the received byte is read by the 80C32. S2B handshake bit which may be interpreted as `request to send'; this is received from the CD-ROM engine UART transmitter and will generate an interrupt to the 80C32 if the TXRDY bit is set and the interrupt is not masked. R/W 7 W R R DATA7 DATA7 - 6 DATA6 DATA6 - 5 DATA5 DATA5 SPR 4 DATA4 DATA4 CPR 3 DATA3 DATA3 TXDRDY 2 DATA2 DATA2 PE 1 DATA1 DATA1 OVRRUN 0 DATA0 DATA0 RXDRDY SPR Table 30 Baud rate generator control: 0xF0C0; note 1 DATA BYTE MNEMONIC BRGSEL Note 1. Register 0xF0C0 controls the S2B UART baud rate and selective inversion of the sub-code information. Control over the parity and the clock doubler is also included together with the ability to invert the sub-code and Q-channel information. R/W 7 R/W C_34_16 6 LOCK 5 4 3 INVQ 2 - 1 ICESEL1 0 ICESEL0 EVENPAR INVSUBC 1996 Jun 19 27 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) Table 31 BRGSEL field description FIELD ICESEL1 to 0 LOGIC 00 01 10 11 INVQ INVSUBC EVENPAR LOCK C_34_16 - - - - - 31.25 kbaud transfer rate 62.5 kbaud transfer rate 187.5 kbaud transfer rate not specified inverts all Q-channel information if set inverts all sub-code information if set selects even parity for S2B UART is set DESCRIPTION SAA7385 read only information; indicates clock synthesizer is stable (after reset) and it is ready to set C_34_16 once LOCK is HIGH, asserting this bit engages the clock doubler Table 32 UART special control register: 0xF09E; note 1 DATA BYTE MNEMONIC UARTCTL Note 1. Register 0xF09E allows the 80C32 UART clock to be derived from 16.945 MHz. This external UART clock is required for reliable operation of the UART if the 80C32 is used for other functions during the transfer. Table 33 UARTCTL field description FIELD DIVIDE5 to 0 LOGIC - DESCRIPTION value 0 produces a 0.264 MHz clock and 58 produces a 2.82 MHz clock for the UART; this is the maximum accepted by the 80C32, a smaller number is required for guaranteed operation e.g. 15 normal UART data input sampled by the external clock select a UART data input sampled by the clock from the internal counter use external UART clock; disables internal clock switch external UART clock input from pin to this internal counter R/W 7 R/W 6 5 DIVIDE5 4 DIVIDE4 3 DIVIDE3 2 DIVIDE2 1 DIVIDE1 0 DIVIDE0 EXTUART UARTCNT UARTCNT EXTUART 0 1 0 1 1996 Jun 19 28 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 9.2 Miscellaneous control registers SAA7385 Table 34 53CF90 direction and audio mode control: 0xF0C1; note 1 DATA BYTE MNEMONIC AUSWP Note 1. Register 0xF0C1 controls the audio mode byte swapping and a test mode bit. Table 35 WTDIR field descriptions FIELD BSB DESCRIPTION Byte swap bit. Defaults to swapping the most significant byte and least significant byte in the audio mode such that the least significant byte of all audio samples is stored at even addresses in the DRAM. Setting this HIGH causes the audio data to be stored in the same way as in the data mode. 4x over-sampling bit selection; default LOW select transmit, or no over-sampling, mode for the sub-code and C-flag UARTs. Setting this bit HIGH will cause the sub-code and C-flag data to be sampled at one quarter the data rate allowing Q-channel information to be correctly stored in the registers while the CD-60 is outputting audio data at 4x over-sampling. Enables internal signals to be multiplexed out when the TEST pin (pin 125) is HIGH. R/W 7 R/W TEST 6 - 5 - 4 - 3 OVER4X 2 BSB 1 - 0 - OVER4X TEST Table 36 SCSI mode control register: 0xF0FD; note 1 DATA BYTE MNEMONIC SCSIMOD Note 1. Register 0xF0FD controls the operation of the interface to the SCSI controller. The outputs of these registers are used to directly control DRAM access cycles, and will affect any current DRAM cycle in progress. Table 37 SCSIMOD field description FIELD BYT/PAG RD_BUF OFF_STR OFF_END OFF_ADR LOGIC 0 1 0 1 0 1 0 1 0 1 SCSI DRAM byte mode access SCSI DRAM page mode access SCSI read/write control; read from buffer memory SCSI read/write control; write to buffer memory SCSI offset start A/B control; select A registers SCSI offset start A/B control; select B registers SCSI offset end A/B control; select A registers SCSI offset end A/B control; select B registers SCSI transfers use only A registers SCSI transfers use A and B registers DESCRIPTION R/W 7 R/W - 6 - 5 - 4 3 2 OFF_STR 1 RD_BUF 0 BYT/PAG OFF_ADR OFF_END 1996 Jun 19 29 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) Table 38 DRAM selection/test mode: 0xF0FE; note 1 DATA BYTE MNEMONIC DRAMSEL Note R/W 7 R/W TEST 6 5 4 3 2 DBL_SPD 1 SAA7385 0 2_DRAMS RESTEST3 to RESTEST0 1_MEG 1. After power-up or reset, DRAMSEL should be the first register that is programmed. This register is used to select the number and the type of DRAMs used. The output of this register is used to control the DRAM access directly and will affect any current DRAM cycle. Table 39 SCSIMOD field description FIELD 2_DRAMS 1_MEG DBL_SPD RESTEST3 to RESTEST0 TEST LOGIC 0 1 0 1 0 1 - single DRAM used two DRAMs used 256 k x 4 1Mx4 single speed refresh; condition after reset double speed refresh; only set if system is running at 0.5 master clock speed reserved for test: enable DRAM access test; switch multiplexer control, enable interrupts DESCRIPTION 0 1 normal operation test mode; read back of RESTEST3 to RESTEST0 is gated by this bit 1996 Jun 19 30 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 10 FRONT-END This Chapter explains the information of the front-end circuitry. 10.1 Minute Second Frame (MSF) addressing and header information SAA7385 Table 40 Header mode and MSF from block decoder: 0xF092, F093, F09A and F09B DATA BYTE MNEMONIC MODE MINS SECS FRMS R/W 7 R R R R 6 5 4 3 2 1 0 MODE7 to MODE0 MINUTES7 to MINUTES0 SECONDS7 to SECONDS0 FRAME7 to FRAME0 These registers contain the mode, minute, second and frame information from the header when in data mode. This data is valid whenever the HDDRDY bit in the RDDSTAT register is set. In audio mode, the MSF address is taken from the Q-channel information. Table 41 Q-channel information: 0xF0A9, F0AA, F0AB, F0B1 and F0B2 DATA BYTE MNEMONIC RDTK RDMD RDMN RDSC RDFM R/W 7 R R R R R 6 5 4 3 2 1 0 TRACK7 to TRACK0 MODE7 to MODE0 ABSMIN7 to ABSMIN0 ABSSEC7 to ABSSEC0 ABSFRM7 to ABSFRM0 These registers contain the information taken from the raw sub-channel information from the CD decoder. Due to the fact that this data has not had any error correction applied to it, it is necessary to perform a CRC check for validity. Twelve bytes of Q-channel information are assembled from each sector of data; the last two bytes contain the CRC parity. Therefore the validity of the contents of these registers can only be determined after the last bit has been loaded and checked. Table 42 Times from QCHRDY to BADQ (RDDSTAT) SPEED n=1 n=2 n=4 n=6 n=8 TIME (s) 2177 1089 545 363 273 For example, at the n = 4 data rate, the BADQ flag (in RDDSTAT) should be checked 545 s after the QFRMRDY interrupt (from RDDSTAT) is asserted. If BADQ is LOW then the contents of the Q-channel registers are valid; otherwise the CRC check failed and the Q-channel information may be incorrect. If the data clock is running (ECMD LOW or ENABRED HIGH) then BADQ will be valid until the end of the sector; otherwise BADQ is valid until the end of the next Q frame. 1996 Jun 19 31 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 10.2 Front-end status and control SAA7385 Table 43 Front-end control: 0xF0BB; note 1 DATA BYTE MNEMONIC FECTL Note 1. Register 0xF0BB controls the front-end of the SAA7385. The naming convention used here is similar to that used in the block decoders. Table 44 FECTL field description FIELD ECMD LOGIC 0 1 SYNASYN 0 1 AUDMODE 0 1 ENABRED 0 1 RWMD - DESCRIPTION Data is shifted in and stored when the next synchronization pattern is detected; (SYNASYN = 1 and AUDMODE = 0). Data flow stop just before next synchronization pattern. ECMD is set on a reset condition; (SYNASYN = 1). Synchronous/asynchronous selection; this controls the method by which data is started and stopped by the block decoder, only operates in data mode. Causes a `panic stop'. A partial frame will reside in current and subsequent buffers unless SIM_EOF is set then cleared; (ECMD = 1). Data is started and stopped on frame boundaries (on synchronization patterns). Data mode. Cleared on reset. Audio mode, where the bit clock is shifted to accommodate EIAJ format. HQRDY in INTRFLG follows HDRRDY in data mode and QFRMDRY in audio mode. Enable red book to data path; while in audio mode, this is equivalent to ECMD in the data mode. No asynchronous stop is provided in the audio mode. Data flow will stop when the next F1 C-flag is detected. Cleared on a reset condition. Red book data is input to buffer after the detection of the next F1 C-flag. This must be pulsed HIGH then LOW every 212 ms to prevent the watch-dog timer from resetting the SAA7385 and the drive. The length of the reset pulse is 967 s. If RWMD is set, the watch-dog timer is disabled. When set, the S2B UART transmitter output is held HIGH. When the pulse is HIGH then LOW, the block decoder begins to search for a synchronization pattern in the data bitstream. Once a synchronization pattern is found, MODE, MINS, SECS, and FRMS become valid. This provides a firmware reset to the frame sequencer and parts of the buffer manager. This would be required if an asynchronous stop of the data stream occurs. Pulsing this HIGH then LOW resets all counters and establishes a `beginning of frame' state. DCOACT in RDDSTAT must be LOW to allow SIM_EOF to have any effect. If SIM_EOF is set, no data or sub-code is stored in the buffer. R/W 7 R/W SIM_EOF 6 RSMD 5 BREAK 4 RWMD 3 2 1 0 ECMD ENABRED AUDMODE SYNASYN BREAK RSMD - - SIM_EOF - 1996 Jun 19 32 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) Table 45 Read status register: 0xF0C3; note 1 DATA BYTE MNEMONIC RDDSTAT Note R/W 7 R DCOTACT 6 BADQ 5 4 3 2 1 SAA7385 0 SYNCERR QFRMRDY HDRRDY HDRERR CRCERR DATERR 1. The information in register 0xF0C3 is a copy of the status byte written to the data buffer at the end of every frame. SYNCERR, DATERR and CRCERR are essentially unusable since they are valid only long enough to be written to the buffer. Table 46 RDDSTAT field description FIELD SYNCERR DATERR CRCERR HDRERR LOGIC 0 0 0 0 1 HDRRDY - DESCRIPTION Good synchronization detected (valid for 120 ns at the end of a sector). Good data (valid for 120 ns at the end of a sector). Good CRC (valid for 120 ns at the end of a sector). Good header. If the automatic storage is selected, assertion of HDRERR inhibits data storage. EFAB during reception of header (valid while HDRRDY set). If the automatic storage is selected, assertion of HDRERR inhibits data storage. When set, a valid header is available. If the header is not read within a frame time, this remains set until the next synchronization pattern and will be set again when the next header arrives. It is cleared when any of the header bytes are read. This bit generates an interrupt to the microcontroller when in data mode. When set, all ten Q-channel bytes are received waiting to be read (BADQ is known). It is reset at the end of frame or when any of the Q-channel bytes are read. This bit generates an interrupt to the microcontroller when in audio mode. If Q-channel information failed CRC then BADQ is set. It is reset on next good CRC check or on end of frame if DCOACT is running. If DCOACT is not running (i.e. audio mode) BADQ is reset on next detection of sub-code gap. If AUTOSTR in WTDIR is selected, assertion of BADQ inhibits audio data storage. Set when data is being shifted an and stored in the buffer: this will remain HIGH for the entire transmission. QFRMRDY - BADQ - DCOTACT - 1996 Jun 19 33 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 11 BUFFER MANAGER 11.1 Front-end to buffer manager interface SAA7385 The buffer manager interface to the front-end is write only with no handshaking. The front-end passes one byte of data and a write strobe to the buffer manager; this byte will be one of five types of data (see Table 47). The data byte is latched and the interface is given the highest priority thus no wait signal is required. The other signals passed from the front-end logic are an end-of-frame strobe (which is the same as the status byte write strobe), a software-generated reset pulse (used to reset the front-end counters), and a reset pulse for the Q-channel and sub-code offset counters. The buffer manager provides the remainder of the logic to write the data into the RAM and keep track of the frame addresses and offset addresses. This logic consists of a 12-bit frame offset counter FEOFF, for data and an 9-bit frame counter; this is a relative frame number and is not related to the CD-ROM frame number. Offset counters are also provided for the four other types of data. The other offset address generators are based on fixed addresses, and they will be loaded with the start address at the beginning of each frame. The five types of data from the front-end are loaded into the frame map as shown in Table 47. Table 47 Data types from the front-end START 0x000 0x930 0x940 0x9A0 0xBDE END 0x92F 0x93F 0x99F 0xAC5 0xBDE LENGTH 0x930 0x010 0x060 0x126 0x001 header, data and parity Q-channel sub-channel error flags status byte DATA TYPE Initially the front-end frame counter and all of the offset counters are cleared by reset or loaded with the contents of FEFRM# when the last frame as specified by LASTFRM is filled; therefore FEFRM# should be loaded with the required starting frame number. The data frame offset counter, FEFRMOFF, may be loaded for test purposes, but is cleared at the end of each frame. LASTFRM establishes the limit of the frame memory. This register should be loaded with the required number of frames; the amount of memory used is 3 kbytes times the number of frames. The front-end frame address counter uses this value to determine the correct location to clear the counter. Once the data load process starts, the offset counter (FEFRMOFF) increments after each byte is written into memory. This process continues until an end of frame signal is received from the front-end logic. If an error occurs and the offset counter increments past the maximum 2352, an interrupt will be issued to the microcontroller. Table 48 Front-end frame offset: 0xF0E2, F0E3 DATA BYTE MNEMONIC FEFRMOFF FEFRMOFF R/W 7 R/W R/W - - - 6 5 4 - 3 2 1 0 OFFSET7 to OFFSET0 OFFSET11 to OFFSET8 This register allows the front-end frame offset counter to be read and reloaded. The counter associated with these registers is loaded after the most significant byte is written; the least significant byte must be written first to ensure that the counter is loaded correctly. If a DRAM access is in progress that uses the address from the counter, the update will be delayed until the access is complete. This counter is cleared on reset or after each frame is loaded into buffer memory. Therefore, this register should not be loaded during normal operation. 1996 Jun 19 34 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) Table 49 Front-end frame number: 0xF0E4, F0E5 DATA BYTE MNEMONIC FEFRM# FEFRM# R/W 7 R/W R/W NUM7 - 6 NUM6 - 5 NUM5 - 4 NUM4 - 3 NUM3 - 2 NUM2 - SAA7385 1 NUM1 - 0 NUM0 NUM8 This register allows the front-end frame number counter to be read and reloaded. The counter associated with these registers is loaded after the most significant byte is written; the least significant byte must be written first to ensure that the counter is loaded correctly. If a DRAM access is in progress that uses the address from the counter, the update will be delayed until the access is completed. This counter is cleared on reset or when the last frame, as specified by LASTFRM, is filled. Therefore, this register should only be loaded if a non-zero start frame number is required. The frame counter is automatically cleared at the end of the frame buffer memory and thus multiple passes of a non-zero start address will require a re-load for each pass; it is not practical to do this in real-time. Table 50 Last frame number for storage: 0xF0F8, F0F9 DATA BYTE MNEMONIC LASTFRM LASTFRM R/W 7 R/W R/W NUM7 - 6 NUM6 - 5 NUM5 - 4 NUM4 - 3 NUM3 - 2 NUM2 - 1 NUM1 - 0 NUM0 NUM8 These registers are used by the buffer manager to set the top of frame storage memory (wrap point). Any memory past this point is available for general usage by the microcontroller. The outputs of the registers are used directly to control DRAM access cycles, and will affect any current DRAM cycle in progress. Both the SCSI address counter and the front-end frame address counter use this value to determine the correct location to clear their respective frame counters. 11.2 Microcontroller to buffer manager interface The microcontroller interface allows the microcontroller to read or write any register or the frame store memory. Frame and offset registers are used to update the counters after the most significant byte has been loaded. Frame store memory is addressed using a frame number register controller by the microcontroller. Logic is provided to allow the frame number of the last complete frame received (LSTCMPFM) from the front-end to be read by the microcontroller for the purpose of setting the microcontroller frame address. Memory beyond the last frame number is available to the microcontroller using the microcontroller bottom 32 kbyte located at 0x0000 to 0x7FFF. The 4 kbyte segment at 0x8000 to 0x8FFF is used to address the current frame memory. Also, the next frame may be accessed at 0x9000 to 0x9FFF, and the current frame plus 2 may be accessed at 0xA000 to 0xAFFF. A page register is provided to allow the microcontroller to address the complete memory range in 32 kbyte pages. All microcontroller accesses to memory are single byte read or write cycles. All microcontroller accesses to memory will generate a wait state. If no other accesses to memory are in progress then a minimum wait state cycle will be generated. If, however, other cycles are in progress then the microcontroller is forced to wait until the lower priority access cycles finish and any high priority access cycles are completed. The worst case wait is four complete access cycles; a total of 20 clock cycles in byte mode and 32 cycles in nibble mode. 1996 Jun 19 35 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) Table 51 Last complete frame number: 0xF0E6, F0E7 DATA BYTE MNEMONIC LSTCMPFM LSTCMPFM 11.3 R/W 7 R R NUM7 - 6 NUM6 - 5 NUM5 - 4 NUM4 - 3 NUM3 - 2 NUM2 - SAA7385 1 NUM1 - 0 NUM0 NUM8 ECC to buffer manager interface The ECC logic is able to access the buffer manager frame memory in either byte or burst mode. The ECC logic provides an offset address and uses a frame address programmed by the microcontroller, ECCFRM#. The logic can write a single byte or variable number of bytes. In the event of an access to a variable number of bytes, the ECC logic will assert the signal BURST and EREQ to indicate that a large number of cycles are requested. For each read or write cycle, the buffer manager will toggle EACK HIGH for one clock cycle to indicate that one byte of data has been read from or written to the memory. A single byte cycle will be the same with the exception that BURST will remain negated (LOW). In the event of a higher priority memory access request during a burst cycle, EACK will remain LOW for the duration of the higher priority access cycle. At the end of the higher priority access, the burst cycle will resume and EACK will again toggle HIGH after each read or write is completed. Table 52 ECC frame number address registers: 0xF0F4, F0F5; notes 1 and 2 DATA BYTE MNEMONIC ECCFRM# ECCFRM# Notes 1. These registers provide the frame number address for ECC access to memory. The counter associated with these registers is loaded after the most significant byte is written; the least significant byte must be written first to ensure that the counter is loaded correctly. If a DRAM access is in progress that uses the address from the counter, the update will be delayed until the access is completed. 2. ECCFRM# is used to determine the frame address for all ECC operations. This register must be reloaded for each frame accessed by the ECC. 11.4 SCSI to buffer manager interface The transfer block is specified by registers SCSIOFFS and SCSIOFFE. For each frame, the transfer will start at the address specified by SCSIOFFS and continue until the address specified by SCSIOFFE is transferred. After each block is transferred, the frame address SCSICFRM will be incremented and the transfer will continue with the same address block from the next frame. If OFF_ADR is set, then two blocks of data are transferred. In the two offset mode, both SCSIOFFS and SCSIOFFE are used to access two independent register pairs; for simplicity, these are called the A registers and the B registers. In this event, the transfer for each frame is a two step process. First, the offset block specified by SCSIOFFS-A and SCSIOFFE-A is transferred; the transfer address range is from SCSIOFFS-A to SCSIOFFE-A and includes both the start and end addresses. After the first offset block is 36 R/W 7 R/W R/W NUM7 - 6 NUM6 - 5 NUM5 - 4 NUM4 - 3 NUM3 - 2 NUM2 - 1 NUM1 - 0 NUM0 NUM8 The SCSI registers should be loaded prior to starting an SCSI transfer. The SCSIMOD register should be loaded first. BYT/PAG from this register is used to control the type of DRAM access used by the SCSI interface. If BYT/PAG is HIGH then burst mode access cycles are selected; multiple CAS access cycles are used to access data as fast as possible. RD_BUF from SCSIMOD controls the direction of data flow to the buffer memory; this bit is kept LOW to allow reading of data from the DRAM buffer. If RD_BUF is asserted then SCSI data will be written to the DRAM buffer. OFF_ADR from SCSIMOD is used to select between one and two offset mode for the SCSI transfer. OFF_ADR LOW selects single offset mode in which one block of data is transferred for each frame of the buffer. 1996 Jun 19 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) transferred, the second offset block as specified by SCSIOFFS-B and SCSIOFFE-B is transferred. The frame address will not be incremented until after both offset blocks are transferred. Once both offset blocks are transferred, the frame address is incremented and again the two offset blocks are transferred for the next frame. Reading and writing of the A and the B registers is controlled by an automatic switching after the most significant bytes of the registers are written. After power-up or reset the pointer to the A registers will be selected. If the dual offset mode is selected, the A/B switch will be toggled when the most significant bytes of the registers are written; either the most significant bytes of SCSIOFFS or SCSIOFFE. Any future reads or writes will access the B registers. The process of loading and reading the two SCSI offset address pairs can be monitored and controlled by OFF_STR and OFF_END from SCSIMOD. Reading OFF_STR shows the status of the A/B switch for the SCSIOFFS-A/B registers; reading OFF_END shows the status of the A/B switch for the SCSIOFFE-A/B registers. A write to SCSIMOD with OFF_STR LOW will clear the A/B switch for the SCSIOFFS registers; a write to SCSIMOD with OFF_END LOW will clear the A/B switch for the SCSIOFFE registers. SCSISFRM is used to determine the starting frame address for all SCSI operations. The associated counter is automatically incremented after each frame, and is cleared Table 53 SCSI offset start register (A and B): 0xF0E8, F0E9; note 1 DATA BYTE MNEMONIC SCSIOFFS SCSIOFFS Note R/W 7 R/W R/W - - - 6 5 4 - 3 2 SAA7385 when the last frame as specified by LASTFRM is transferred. To update the SCSI frame address counter, SCSISFRM must be rewritten. The current SCSI frame address is available by reading SCSICFRM. The frame counter is automatically cleared at the end of the frame buffer memory and thus multiple passes of a non-zero start address will require a re-load for each pass; it is not practical to do this in real-time. The SCSIOFFS registers access either one or two register pairs as controlled by SCSIMOD. SCSIOFFS determines the starting offset address for a SCSI transfer. The SCSIOFFE register accesses either one or two register pairs as controlled by SCSIMOD. SCSIOFFE determines the ending offset address for a SCSI transfer. Remarks: * If two offset pairs are used, the A start offset must be written last to ensure that the correct offset start address is loaded into the counter. * In the two offset mode, reading the register after loading is not possible due to the automatic switching feature; if the A offset pair is written, and the register pair is read, the B offset pair would be read. 1 0 OFFSET7 to OFFSET0 OFFSET11 to OFFSET8 1. These registers, together with the offset end registers, allow full control over the number of frame bytes that will be transferred to the SCSI port. 1996 Jun 19 37 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) Table 54 SCSI offset end registers (A and B): 0xF0EA, F0EB; note 1 DATA BYTE MNEMONIC SCSIOFFE SCSIOFFE Note R/W 7 R/W R/W - - - 6 5 4 - 3 2 SAA7385 1 0 OFFSET7 to OFFSET0 OFFSET11 to OFFSET8 1. These registers together with the offset start registers, allow full control over the number of frame bytes that will be transferred to the SCSI port. Table 55 SCSI transfer start frame number: 0xF0EC, F0ED; note 1 DATA BYTE MNEMONIC SCSISFRM SCSISFRM Note 1. This register determines the starting frame number for an SCSI transfer. The outputs of the registers are used to directly control DRAM access cycles, and will affect any current DRAM cycle in progress. The SCSI frame pointer will wrap back to this point. Table 56 SCSI current transfer frame: 0xF0EE, F0EF; note 1 DATA BYTE MNEMONIC SCSICFRM SCSICFRM Note 1. This register allows the current SCSI frame transfer number to be read. 11.5 Miscellaneous buffer manager considerations R/W 7 R R NUM7 - 6 NUM6 - 5 NUM5 - 4 NUM4 - 3 NUM3 - 2 NUM2 - 1 NUM1 - 0 NUM0 NUM8 R/W 7 R/W R/W NUM7 - 6 NUM6 - 5 NUM5 - 4 NUM4 - 3 NUM3 - 2 NUM2 - 1 NUM1 - 0 NUM0 NUM8 The following bandwidth limitation must be observed in normal operation: * All burst mode operations (SCSI and ECC) take twice as long in nibble mode, and single cycle operations take 60% longer; 236 ns compared with 147.5 ns. For this reason, operation of the DRAM interface at the maximum 8 times transfer rate in nibble mode is not supported. * In byte mode, only 833 ns is available between each data write from the front-end at the maximum 8 times transfer rate. At the end of the frame, multiple front-end byte writes may stack up and therefore it is recommended that the 80C32 avoids DRAM access at the end of the frame. If two SCSI offset pairs are used, the A start must be written last to ensure that the correct offset start address is loaded into the counter. In the two SCSI offset mode, reading the register after loading is not possible due to the automatic switching feature. 1996 Jun 19 38 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 11.6 53CF94 related registers SAA7385 In the 53CF94 SCSI controller, some registers are read only and others are write only. These share the same address and the multiplexing between the two depends on the read or write select. This part contains only a brief description of the register definitions. For a more detailed definition, see the data sheet for the SCSI device. Table 57 Transfer count registers: 0xF0A4, F0A5 and F0BE- 53CF94 addresses: 0x00, 01, 0E; note 1 DATA BYTE MNEMONIC TCLOW TCMID TCHIGH Note 1. These registers form the 24-bit transfer count value for DMA operations; they specify the number of bytes that are transferred. Table 58 FIFO buffer register: 0xF0A6 - 53CF94 address 0x02; note 1 DATA BYTE MNEMONIC FIFO Note 1. The FIFO is a 16 x 9-bit buffer between the SCSI interface and the memory. The SCSI command packet will be present in this FIFO ready to be read by the microcontroller at the end of the SCSI command phase. Table 59 Command register: 0xF0A7 - 53CF94 address 0x03; note 1 DATA BYTE MNEMONIC CMD Note 1. The command register is a two-deep read/write register used to pass commands to the SCSI controller; up to two commands can be stacked at the same time. When ENDMA is set, the command is a DMA instruction. Table 60 Status register and destination ID: 0xF0AC - 53CF94 address 0x04; note 1 DATA BYTE MNEMONIC STAT STAT Note 1. This register contains the flags indicating the occurrence of certain events. R/W 7 R W INT - 6 GE - 5 PE - 4 TC - 3 VGC - 2 MSG ID2 1 C/D ID1 0 I/O ID0 R/W 7 R/W ENDMA 6 5 4 3 2 1 0 COMMAND6 to COMMAND0 R/W 7 R/W DATA7 6 DATA6 5 DATA5 4 DATA4 3 DATA3 2 DATA2 1 DATA1 0 DATA0 R/W 7 R/W R/W R/W DATA7 DATA7 DATA7 6 DATA6 DATA6 DATA6 5 DATA5 DATA5 DATA5 4 DATA4 DATA4 DATA4 3 DATA3 DATA3 DATA3 2 DATA2 DATA2 DATA2 1 DATA1 DATA1 DATA1 0 DATA0 DATA0 DATA0 1996 Jun 19 39 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) Table 61 STAT field description FIELD MSG, C/D, I/O VGC TC PE GE INT ID2 to ID0 DESCRIPTION These indicate the phase on the SCSI bus. SAA7385 Valid Group Code; set if the group code matches code defined in ANSI X3.131-1986. Terminate Count; set when transfer count decrements to zero. Parity Error; set if parity checking is enabled and a SCSI parity error occurs. Gross Error; set on various error conditions. These errors do not cause interrupts. Interrupt. Indicates whether device is trying to interrupt the microcontroller. Specifies the encode destination for selection or re-selection. Table 62 Interrupt register and time-out register: 0xF0AD - 53CF94 address 0x05; note 1 DATA BYTE MNEMONIC INT INT Note 1. This register is used in conjunction with STAT and SEQSTP to determine the cause of an interrupt. Table 63 INT field description FIELD SEL SATN RESEL FC BS DIS ILCMD SRST TIMEOUT7 to TIMEOUT0 DESCRIPTION Selected; set during selection phase if selected as a target with ATN negated. Selected with ATN; set during selection if selected as a target with ATN asserted. Reselected; set during reselection phase if reselected as an initiator. Function complete; set after any target mode command has been completed. Bus service. Indicates that another device is requesting service; in target mode it is asserted whenever the initiator asserts ATN. Disconnect. In target mode this is asserted and as a Terminate Sequence or a Command Complete Sequence command causes disconnection. Illegal command; set when a reserved code is placed in CMD or when the command is from a mode group. SCSI reset detect. This may be set if a reset on the SCSI bus is detected. Time-out period for response to selection or re-selection. R/W 7 R W SRST 6 ILCMD 5 DIS 4 BS 3 FC 2 RESEL 1 SATN 0 SEL TIMEOUT7 to TIMEOUT0 Table 64 Sequence step register and synchronous transfer register: 0xF0AE - 53CF94 address 0x06; note 1 DATA BYTE MNEMONIC SEQSTP SEQSTP Note 1. The register fields are described in Table 65. 1996 Jun 19 40 R/W 7 R W - - 6 - - 5 - - 4 - 3 SOM 2 SS2 1 SS1 0 SS0 TRANSPERIOD4 to TRANSPERIOD0 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) Table 65 SEQSTP field descriptions FIELD SS2 to SS0 SOM DESCRIPTION SAA7385 Sequence step. Counter increments at various points in a command; may be used for error recovery. Synchronous offset maximum. When clear, the synchronous offset has reached the maximum value. TRANSPERIOD Synchronous transfer period. Specifies minimum time between successive REQ or ACK pulses. Table 66 FIFO flags and synchronous offset register: 0xF0AF - 53CF94 address 0x07; note 1 DATA BYTE MNEMONIC FIFOFLG FIFOFLG Note 1. The field description for the FIFO flags register is shown in Table 67. Table 67 FIFOFLG field descriptions FIELD FF SS SYNCOFFSET number of bytes in the FIFO duplicates of sequence step register controls handshaking in synchronous transfer mode DESCRIPTION R/W 7 R W SS2 6 SS1 5 SS0 4 FF4 3 FF3 2 FF2 1 FF1 0 FF0 SYNCOFFSET7 to SYNCOFFSET0 Table 68 Configuration registers: 0xF0B4, F0B7, F0BC and F0BD - 53CD94 addresses 0x08, 0B, 0C and 0D; note 1 DATA BYTE MNEMONIC CONFIG1 CONFIG2 CONFIG3 CONFIG4 Note 1. The registers described allows the controller to be configured for the specific mode of operation. R/W 7 R/W R/W R/W R/W SLOW RFB IMRC - 6 SRD FE QTE - 5 PTEST EBC CDB10 - 4 PCHK DHZ FSCSI - 3 CTEST SCSI2 FCLK - 2 BPA SRB EAN 1 RPE ADMA TEST 0 DPE T8 BBTE MYBUSID2 to MYBUSID0 1996 Jun 19 41 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) Table 69 CONFIG1 to CONFIG4 field descriptions FIELD MyBusID CTEST PCHK PTEST SRD SLOW DPE RPE BPA SCSI2 DHZ EBC FE RFB T8 ADMA SRB FCLK FSCSI CDB10 QTE IMRC BBTE TEST EAN ID of SCSI controller chip test mode enable enable parity checking parity test mode SCSI reset reporting interrupt disable slow cable mode DMA parity enable register parity enable target bad parity abort allows support for SCSI-2 features DREQ high impedance enable byte control features enable reserve FIFO byte threshold eight alternate DMA mode save residual byte fast clock fast SCSI allows 10-byte group-2 commands to be recognized queue tag enable ID message reserve check back-to-back transfer enable transfer count test mode enable active negation DESCRIPTION SAA7385 Table 70 Clock conversion factor: 0xF0B5 - 54CF94 address 0x09; note 1 DATA BYTE MNEMONIC CLOCK Note 1. This register must be set in accordance with the clock input frequency. Table 71 CLOCK Field Descriptions FIELD CONVERT7 to CONVERT0 clock conversion factor DESCRIPTION R/W 7 W - 6 - 5 - 4 - 3 - 2 1 0 CONVERT7 to CONVERT0 1996 Jun 19 42 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) Table 72 Test Register: 0xF06 - 53CF94 address 0x0A; note 1 DATA BYTE MNEMONIC TEST Note R/W 7 R/W - 6 - 5 - 4 - 3 - 2 HI-Z SAA7385 1 INIT 0 TAR 1. This register is enabled by setting the test mode in CONFIG1; after test mode is entered, a hardware reset or reset command must occur before normal operation may resume. Table 73 TEST field descriptions FIELD TAR INIT HI-Z target mode initiator mode all outputs set to high impedance DESCRIPTION Table 74 FIFO Bottom: 0xFBF - 53CF94 address 0x0F; note 1 DATA BYTE MNEMONIC FIFOBTM Note 1. This register is used during initiator synchronous data in to align 16-bit DMA transfers to word boundaries. R/W 7 W DATA7 6 DATA6 5 DATA5 4 DATA4 3 DATA3 2 DATA2 1 DATA1 0 DATA0 1996 Jun 19 43 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 12 FRAME BUFFER ORGANIZATION Table 75 Frame buffer organization DECIMAL START 0 12 16 2064 2068 2076 2248 2352 2368 2464 2758 2762 2934 3038 END 11 15 2063 2067 2075 2247 2351 2367 2463 2757 2761 2933 3037 3038 LEN 12 4 2048 4 8 172 104 16 96 294 4 172 104 1 START 000 00C 010 810 814 81C 8C8 930 940 9A0 AC6 ACA B76 BDE HEXADECIMAL SAA7385 DATA END 00B 00F 80F 813 81B 8C7 92F 93F 99F AC5 AC9 B75 BDD BDE LEN 00C 004 800 004 008 0AC 068 010 060 126 004 0AC 068 001 synchronization field header frame data CRC parity padding P parity Q parity Q channel sub-channel error flags CRC remainder P syndromes Q syndromes status Table 76 ECC RAM organization BYTE NUMBER DEC 000 204 208 340 344 564 568 572 576 580 584 588 HEX 3 000 0CC 0D0 154 158 234 238 23C 240 244 248 588 psyn[00].s1 psyn[51].s1 psyn[52].s1 psyn[85].s1 flags[071] flags[291] unused[1] crc_rem[3] header[3] ecc_reg[03] ecc_reg[07] ecc_reg[11] 2 psyn[00].s0 psyn[51].s0 psyn[52].s0 psyn[85].s0 flage[070] flage[290] unused[0] crc_rem[2] header[2] ecc_reg[02] ecc_reg[06] ecc_reg[10] 1 qsyn[00].s1 qsyn[51].s1 flags[001] flags[067] flags[069] flags[289] flags[293] crc_rem[1] header[1] ecc_reg[01] ecc_reg[05] ecc_reg[09] 0 qsyn[00].s0 qsyn[51].s0 flags[000] flags[066] flags[068] flags[288] flags[292] crc_rem[0] header[0] ecc_reg[00] ecc_reg[04] ecc_reg[08] 1996 Jun 19 44 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 13 SUMMARY OF CONTROL REGISTER MAP Table 77 Control register map for the SAA7385 ADDRESS F085 F086 F08E F091 F092 F093 F09A F09B F09E F09F F0A1 F0A2 F0A3 F0A4 F0A5 F0A6 F0A7 F0A9 F0AA F0AB F0AC F0AD F0AE F0AF F0B1 F0B2 F0B3 F0B4 F0B5 F0B6 F0B7 F0B9 F0BA F0BB F0BC F0BD F0BE F0BF F0C0 1996 Jun 19 MNEMONIC ECCCTL ECCSTAT NUM_COR CLKSEL MODE FRMS SECS MINS UARTCTL PRGMEM WTS2B RDS2B S2BSTAT TCLOW TCMID FIFO CMD RDTK RDMD RDMN STAT INT SEQSTP FIFOFLG RDSC RDFM WTPWM CONFIG1 CLOCK TEST CONFIG2 WTGCTL RDSW FECTL CONFIG3 CONFIG4 TCHIGH FIFOBTM BRGSEL READ/WRITE R/W R R W R R R R R/W R/W W R R R/W R/W R/W R/W R R R R/W R/W R/W R/W R R R/W R/W W W R/W W R R/W R/W R/W R/W W R/W ECC control register ECC status register ECC register for the number of corrections start the clock synthesizer (doubler) header mode byte from block decoder header frame byte from block decoder header seconds byte from block decoder header minutes byte from block decoder UART special control registers program memory control registers S2B UART transmit buffer S2B UART receive buffer S2B UART status register 53CF94 (00); transfer counter low 53CF94 (01); transfer counter middle 53CF94 (02); FIFO 53CF94 (03); command register Q channel track number Q channel mode number Q channel minutes number (absolute) 53CF94 (04); status register and destination ID 53CF94 (05); interrupt register and time-out DESCRIPTION SAA7385 53CF94 (06); sequence step and synchronous transfer period 53CF94 (07); FIFO flags and synchronous offset Q channel seconds (absolute) Q channel frames (absolute) pulse width modulator duty cycle select 53CF94 (08); configuration register number 1 53CF94 (09); clock conversion factor 53CF94 (0A); test mode 53CF94 (0B); configuration register number 2 GLIC control registers (audio control) drive control switches register front-end control register 53CF94 (0C); configuration register number 3 53CF94 (0D); configuration register number 4 53CF94 (0E); transfer count high and SCSI ID 53CF94 (0F); FIFO bottom baud rate generator select register 45 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) ADDRESS F0C1 F0C2 F0C3 F0C9 F0D8 F0E2 F0E3 F0E4 F0E5 F0E6 F0E7 F0E8 F0E9 F0EA F0EB F0EC F0ED F0EE F0EF F0F4 F0F5 F0F6 F0F7 F0F8 F0F9 F0FB F0FC F0FD F0FE F0FF MNEMONIC AUSWP GPIOCTL RDDSTAT RDJMPRS FSTEST FEFRMOFF FEFRMOFF FEFRM# FEFRM# LSTCMPFM LSTCMPFM SCSIOFFS SCSIOFFS SCSIOFFE SCSIOFFE SCSISFRM SCSISFRM SCSICFRM SCSICFRM ECCFRM# ECCFRM# MICFRM# MICFRM# LASTFRM LASTFRM INTRMSK INTRFLG SCSIMOD DRAMSEL PAGEREG READ/WRITE R/W R/W R R R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W audio byte swap control general purpose bits control register data status register option jumper register frequency synthesizer test register front-end 8 LSBs; frame offset front-end 4 MSBs; frame offset (bit 0 to bit 3) front-end 8 LSBs of the frame front-end 3 MSBs of the frame (bit 0 to bit 2) 8 LSBs; last complete frame number DESCRIPTION SAA7385 3 MSBs; last complete frame number (bit 0 to bit 2) SCSI 8 LSBs; offset start (A and B) SCSI 4 MSBs; offset start (bit 0 to bit 3) SCSI 8 LSBs; offset end (A and B) SCSI 4 MSBs; offset end (bit 0 to bit 3) SCSI 8 LSBs; start transfer frame number SCSI 3 MSBs; start frame number (bit 0 to bit 2) SCSI 8 LSBs; current frame number SCSI 3 MSBs; current frame number (bit 0 to bit 2) ECC 8 LSBs; frame number (frame address) ECC 3 MSBs; frame number (bit 0 to bit 2) microcontroller 8 LSBs; frame number (frame address) microcontroller 3 MSBs; frame number (bit 0 to bit 2) last frame number for storage 8 LSBs last frame number 3 MSBs (bit 0 to bit 2) interrupt mask register interrupt flag register SCSI mode control DRAM selection/test mode register. 80C32 linear address page register 1996 Jun 19 46 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 14 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD Vi(max) Vo Tstg digital supply voltage maximum input voltage on any pin output voltage on any output storage temperature PARAMETER -0.5 VSS - 0.5 -0.5 -55 MIN. +7 VDD + 0.5 +7 +150 MAX. SAA7385 UNIT V V V C 15 OPERATING CHARACTERISTICS 15.1 I2S-bus timing; data mode VDD = 4.75 to 5.25 V; VSS = 0 V; Tamb = -10 to +70 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT I2S-bus timing (single speed x n); see Fig.13 and note 1 CLOCK INPUT: CLAB Tcy output clock period sample rate = fs sample rate = 2 fs sample rate = 4 fs tCH clock HIGH time sample rate = fs sample rate = 2fs sample rate = 4fs tCL clock LOW time sample rate = fs sample rate = 2fs sample rate = 4fs INPUTS: DAAB, WSAB AND EFAB tsu set-up time sample rate = fs sample rate = 2fs sample rate = 4fs th hold time sample rate = fs sample rate = 2fs sample rate = 4fs Note 1. The I2S-bus timing is directly related to the overspeed factor `n' in the normal operating mode. In the lock-to-disc mode `n' is replaced by the disc speed factor `d'. 95/n 48/n 24/n 95/n 48/n 24/n - - - - - - - - - - - - ns ns ns ns ns ns - - - 166/n 83/n 42/n 166/n 83/n 42/n 472.4/n 236.2/n 118.1/n - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns 1996 Jun 19 47 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 15.2 EIAJ timing; audio mode VDD = 4.75 to 5.25 V; VSS = 0 V; Tamb = -10 to +70 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. SAA7385 MAX. UNIT EIAJ timing (single speed x n); see Fig.14 and note 1 CLOCK INPUT: CLAB Tcy output clock period sample rate = fs sample rate = 2 fs sample rate = 4 fs tCH clock HIGH time sample rate = fs sample rate = 2fs sample rate = 4fs tCL clock LOW time sample rate = fs sample rate = 2fs sample rate = 4fs INPUTS: DAAB, WSAB AND EFAB tsu set-up time sample rate = fs sample rate = 2fs sample rate = 4fs th hold time sample rate = fs sample rate = 2fs sample rate = 4fs Note 1. The EIAJ timing is directly related to the overspeed factor `n' in the normal operating mode. In the lock-to-disc mode `n' is replaced by the disc speed factor `d'. 95/n 48/n 24/n 95/n 48/n 24/n - - - - - - - - - - - - ns ns ns ns ns ns - - - 166/n 83/n 42/n 166/n 83/n 42/n 472.4/n 236.2/n 118.1/n - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns 1996 Jun 19 48 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) SAA7385 handbook, full pagewidth CLAB DAAB 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WSAB left right EFAB (error flags) left LSB valid right MSB valid clock period Tcy tCL tCH right LSB valid VDD - 0.8V CLAB 0.8 V th DAAB WSAB EFAB tsu VDD - 0.8 V 0.8 V MGE399 Fig.13 I2S-bus timing diagram. handbook, full pagewidth CLAB DAAB 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WSAB EFAB clock period Tcy left right tCL tCH VDD - 0.8V CLAB 0.8 V th DAAB WSAB EFAB tsu VDD - 0.8 V 0.8 V MGE400 Fig.14 EIAJ timing diagram. 1996 Jun 19 49 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 15.3 R-W timing (see Fig.15) 15.4 C-flag timing (see Fig.16) SAA7385 The data from sub-code R-W may be read via the V4 pin from the CD-decoder and has a format similar to RS232. The sub-code synchronization word is formatted by a pause of 200 s minimum. Each sub-code byte starts with a logic 1 followed by seven bits (Q to W). The gap between bytes is variable between 1.3 and 90 s. A 1-bit flag signal is input to the CFLAG pin. This signal shows the status of the error corrector and interpolator and is updated every frame. handbook, full pagewidth 200 s min W96 1 11.3 s Q1 R1 S1 T1 U1 V1 W1 11.3 s min 90 s max 1 MGE401 Fig.15 Sub-code formatting and timing from the V4 pin. handbook, full pagewidth 11.3 s F1 F2 F3 F4 F5 F6 F7 45.4 s (nominal speed) MGE402 Fig.16 C-flag output timing. 1996 Jun 19 50 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 15.5 S2B interface timing SAA7385 The S2B serial interface consists of four lines (see Fig.17): Transmit data (TXD) Receive data (RXD) Data path ready to accept data; active LOW (CPR) Basic engine ready to accept data; active LOW (SPR). These are used for communication. TXD and CPR for sending acknowledges and information data to the data path and RXD and SPR for receiving commands and parameters from the data path. The data is transferred frame-wise and asynchronously. A data frame is proceeded by a start-bit (active LOW), followed by the actual data byte, and again followed by a parity bit (even parity), and a stop bit (active HIGH), see Fig.18. In total, eleven bits per frame are incorporated. The interface is full duplex, meaning data frames may be transmitted and received simultaneously. The bit-rate is selectable: 187.5 kbits/s with a 2.6% error 62.5 kbits/s with a 0.4% error 31.25 kbits/s with a 0.4% error. data path handbook, halfpage RXD CPR TXD SPR sequoia basic engine TXD CPR RXD SPR MGE403 Fig.17 S2B interface. handbook, halfpage TXD S0 0 1 2 3 4 5 6 7 P S1 CPR MGE404 Fig.18 S2B Timing. 1996 Jun 19 51 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 15.6 SCSI interface timing VDD = 4.75 to 5.25 V; VSS = 0 V; Tamb = -10 to +70 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. - 40 - 40 MAX. SAA7385 UNIT Target asynchronous send; see Fig.19 t1 t2 t3 t4 t1 t2 t3 t4 Data set-up time to REQ LOW ACK LOW to REQ HIGH Data hold time from ACK LOW ACK HIGH to REQ LOW FIFO not empty data already set-up 60 - 5 - - FIFO not full - 0 0 ns ns ns ns Target asynchronous receive; see Fig.20 ACK LOW to REQ HIGH ACK HIGH to REQ LOW Data set-up time to ACK LOW Data hold time from REQ HIGH 40 40 - - ns ns ns ns Fast SCSI-2 single-ended transfers (10 Mbytes/s) TARGET SYNCHRONOUS OUTPUT; see Fig.21 t1 t2 t3 t4 t1 t2 t3 t4 REQ or ACK assertion period REQ or ACK negation period Data set-up time to REQ or ACK LOW Data hold time from ACK or REQ LOW 35 35 33 45 - - - - - - - - ns ns ns ns TARGET SYNCHRONOUS INPUT; see Fig.22 REQ or ACK assertion period REQ or ACK negation period Data set-up time to REQ or ACK LOW Data hold time from ACK or REQ LOW 20 20 0 10 ns ns ns ns handbook, full pagewidth SD7 to SD0 t1 REQ t2 ACK MGE407 t3 t4 Fig.19 Target asynchronous send signal transitions. 1996 Jun 19 52 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) SAA7385 handbook, full pagewidth REQ t1 ACK t3 SD7 to SD0 MGE408 t2 t4 Fig.20 Target asynchronous receive signal transitions. handbook, full pagewidth SD7 to SD0 t3 REQ/ACK t1 t4 t2 MGE409 Fig.21 Target synchronous output. handbook, full pagewidth SD7 to SD0 t3 REQ/ACK t1 t4 t2 MGE410 Fig.22 Target synchronous input. 1996 Jun 19 53 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 15.7 Microprocessor interface VDD = 4.75 to 5.25 V; VSS = 0 V; Tamb = -10 to +70 C; unless otherwise specified. SYMBOL PARAMETER MIN. - - - - 65 - 30 130 6 MAX. SAA7385 UNIT Program memory fetch timing; see Fig.23 tAVLL tLLAX tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ address valid to ALE LOW address hold after ALE LOW ALE LOW to PSEN LOW PSEN pulse width PSEN LOW to valid input instruction Input instruction hold after PSEN Input instruction float after PSEN address to valid input instruction PSEN low to address float 15 35 25 80 - 0 - - - ns ns ns ns ns ns ns ns ns handbook, full pagewidth tAVLL + tLLPL tPLPH tPLIV PSEN tLLAX + tAVLL tPLAZ LA7 to LA0 tAVIV A15 to A8 MGE411 tPXIZ tPXIX Fig.23 Program code fetch cycle. 1996 Jun 19 54 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 15.8 DRAM interface (the SAA7385 is designed to operate with standard 70 ns DRAMs) VDD = 4.75 to 5.25 V; VSS = 0 V; Tamb = -10 to +70 C; unless otherwise specified. SYMBOL PARAMETER - 55 0 0 - 15 20 15 3 10 - 5 70 5 20 15 55 0 3 40 note 1 - 15 10 70 70 35 130 20 0 0 - 50 0 0 20 n/a(1) MIN. MAX. SAA7385 UNIT DRAM interface timing; see Figs 24 to 28 tacc;CA thCA;RAS tsu;CA tsu;RA tacc;CAS th;CA tW;CAS th;CAS tCASLZ tpCAS tacc;pCAS tpCAS;RAS th;CAS tsu;CAS twCASL th;DAT thDAT;RAS tsu;DAT td;OFF tcy;FPR/W tcy;FPR-W tacc;RAS tdRAS;CA th;RA tW;RAS tW;RASFP tCA;RASL tcy;R/W tdRAS;CAS tsu;R thrR;CAS tREF tpRAS tpRAS;CAS thr;RAS th;RAS tcy;R-W access time from column address column address hold time from RAS column address set-up time row address set-up time access time from CAS column address hold time CAS pulse width CAS hold time (CBR refresh) CAS to output in low impedance CAS precharge time access time from CAS precharge CAS to RAS precharge time CAS hold time CAS set-up time (CBR refresh) write command to CAS lead time data input hold time data input hold time from RAS data input set-up time output buffer turn off delay fast page mode read or write cycle time fast page mode read-write cycle time access time from RAS RAS to column address delay time row address hold time RAS pulse width RAS pulse width (fast page mode) column address to RAS lead time random read or write cycle time RAS to CAS delay time read command set-up time read command hold time (referenced to CAS) refresh period RAS precharge time RAS to CAS precharge time read command hold time (referenced to RAS) RAS hold time read-write cycle time 35 - - - 20 - 10000 - - - 40 - - - - - - - 20 - - 70 35 - 10000 100000 - - 50 - - 32 - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1996 Jun 19 55 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) SYMBOL tRASL;W ttrans thW thW;RAS tsu;WE tW;W th;WE tsu;WE Note 1. Not applicable. PARAMETER write command to RAS lead time transition time (rise or fall) write command hold time write command hold time (referenced to RAS) WE command set-up time write command pulse width WE hold time (CBR refresh) WE set-up time (CBR refresh) 20 3 15 55 0 15 10 10 MIN. - 50 - - - - - - MAX. SAA7385 UNIT ns ns ns ns ns ns ns ns handbook, full pagewidth tcy;R/W tW;RAS tpRAS RAS th;CAS tpCAS;RAS tdRAS;CAS th;RAS tW;CAS CAS thCA;RAS tdRAS;CA tsu;RA th;RA tsu;CA th;CA tCA;RASL ADDRESS ROW COLUMN tacc;CA tacc;RAS tacc;CAS tCASLZ ROW td;OFF DATA MGE412 Fig.24 DRAM read cycle. 1996 Jun 19 56 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) SAA7385 handbook, full pagewidth tcy;R/W tW;RAS tpRAS RAS th;CAS tpCAS;RAS tdRAS;CAS th;RAS tW;CAS CAS thCA;RAS tdRAS;CA tsu;RA th;RA tsu;CA th;CA tCA;RASL ADDRESS ROW COLUMN thDAT;RAS th;DAT ROW tsu;DAT DATA MGE413 Fig.25 DRAM early write cycle. 1996 Jun 19 57 andbook, full pagewidth 1996 Jun 19 tW;RASFP th;CAS tcy;FPR/W tW;CAS tpCAS tW;CAS tpCAS th;RAS tW;CAS th;CA tsu;CA tsu;CA th;CA tCA;RASL th;CA Philips Semiconductors RAS tpCAS;RAS tdRAS;CAS CAS thCA;RAS tdRAS;CA tsu;RA th;RA tsu;CA Error correction and host interface IC for CD-ROM (SEQUOIA) 58 COLUMN tacc;CA tacc;pCAS tacc;CAS td;OFF tCASLZ tacc;CAS tCASLZ tacc;pCAS td;OFF tacc;CA COLUMN COLUMN tacc;CA tacc;pCAS tacc;CAS tCASLZ td;OFF MGE414 ADDRESS ROW DATA Preliminary specification SAA7385 Fig.26 Fast page mode DRAM read cycle. Philips Semiconductors tW;RAS andbook, full pagewidth 1996 Jun 19 th;CAS tcy;FPR/W tW;CAS tpCAS tW;CAS tpCAS th;RAS tW;CAS th;CA tsu;CA tsu;CA th;CA th;CA tCA;RASL RAS tpCAS;RAS tdRAS;CAS CAS thCA;RAS tdRAS;CA tsu;RA th;RA tsu;CA Error correction and host interface IC for CD-ROM (SEQUOIA) 59 COLUMN COLUMN COLUMN th;DAT th;DAT tsu;DAT tsu;DAT th;DAT MGE415 ADDRESS ROW thDAT;RAS tsu;DAT DATA Preliminary specification SAA7385 Fig.27 Fast page mode DRAM write cycle. Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) SAA7385 handbook, full pagewidth tcy;R/W tW;RAS RAS tpCAS;RAS tpRAS;CAS tpRAS CAS tsu;RA th;RA ADDRESS ROW ROW MGE416 Fig.28 DRAM refresh cycle. 1996 Jun 19 60 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 16 PACKAGE OUTLINE SAA7385 SQFP128: plastic shrink quad flat package; 128 leads (lead length 1.6 mm); body 14 x 20 x 2.8 mm SOT387-2 c y X A 102 103 65 64 e E HE A A2 A1 (A 3) Lp pin 1 index 128 1 wM D HD B vM B 39 38 vMA bp detail X L wM e bp 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.40 A1 min. 0.25 A2 3.05 2.55 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.0 E (1) 14.0 e 0.50 HD 23.2 HE 17.2 L 1.60 Lp 0.95 0.65 v 0.20 w 0.08 y 0.10 7o 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT387-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 96-03-14 1996 Jun 19 61 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 17 SOLDERING 17.1 Introduction 17.3 Wave soldering SAA7385 There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 17.2 Reflow soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 17.4 Repairing soldered joints Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 1996 Jun 19 62 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) 18 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values SAA7385 This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 19 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Jun 19 63 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 805 4455, Fax. +61 2 805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 708 296 8556 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 615 800, Fax. +358 615 80920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 52 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. +30 1 4894 339/911, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 648 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 83749, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 926 5361, Fax. +7 095 564 8323 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil, P.O. Box 7383 (01064-970), Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 2A Akademika Koroleva str., Office 165, 252148 KIEV, Tel. +380 44 476 0297/1642, Fax. +380 44 476 6991 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 825 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996 Internet: http://www.semiconductors.philips.com/ps/ (1) ADDRESS CONTENT SOURCE June 19, 1996 SCA49 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 517021/50/01/pp64 Date of release: 1996 Jun 19 Document order number: 9397 750 00917 |
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